1. Field of the Invention
The present invention relates to DMOS transistors and, more particularly, to a DMOS transistor with a cavity that lies below the drift region.
2. Description of the Related Art
A metal-oxide-semiconductor (MOS) transistor is a well-known device that has heavily-doped source and drain semiconductor regions which are separated by a lightly-doped channel semiconductor region of the opposite conductive type. The MOS transistor also has an oxide layer that lies over the channel semiconductor region, and a metal gate that touches the oxide layer and lies over the channel semiconductor region. In addition to metal, the gate of a MOS transistor is also commonly formed with doped polysilicon.
A double-diffused MOS (DMOS) transistor is a power transistor that has a large lightly-doped drain semiconductor region, known as a drift region, which touches the channel semiconductor region and typically lies between the channel semiconductor region and the heavily-doped drain semiconductor region. DMOS transistors are commonly formed as vertical devices where the source and drain regions are vertically spaced apart, and as lateral devices where the source and drain regions are horizontally spaced apart.
In operation, vertical DMOS transistors typically provide better performance (e.g., a lower on-state drain-to-source resistance) than lateral DMOS transistors. Lateral DMOS transistors, however, are usually much easier to fabricate and, therefore, are less expensive to produce than vertical DMOS transistors.
FIG. 1 shows a cross-sectional diagram that illustrates an example of a conventional lateral DMOS transistor 100. As shown in FIG. 1, DMOS transistor 100 includes a silicon-on-insulator (SOI) structure 102 that includes a bulk region 104, an insulator layer 106 approximately 0.4 μm thick that covers the top surface of bulk region 104, and a single-crystal semiconductor region 108 approximately 0.8 μm thick that touches the top surface of insulator layer 106.
In addition, SOI structure 102 includes a trench isolation structure TOX that extends through single-crystal semiconductor region 108 to touch insulator layer 106 and form a number of isolated regions of single-crystal semiconductor region 108. (Only one isolated region of single-crystal semiconductor region 108 is shown for clarity.)
As further shown in FIG. 1, single-crystal semiconductor region 108 includes a p-type well 110 that touches insulator layer 106, a p− body region 112 that touches p-type well (and sets the threshold voltage of DMOS transistor 100), and an n− drift region 114 that touches insulator layer 106, p-type well 110, and p− body region 112.
Single-crystal semiconductor region 108 additionally includes an n+ drain region 120 that touches n− drift region 114 and lies spaced apart from p− body region 112, an n+ source region 122 that touches p− body region 112 and lies spaced apart from n− drift region 114, and a p+ contact region 124 that touches p− body region 112. Thus, n− drift region 114 touches a doped region that includes p-type well 110, p− body region 112, and p+ contact region 124. Also, a channel region 126 of p− body region 112 lies horizontally between and touches n− drift region 114 and n+ source region 122.
As additionally shown in FIG. 1, lateral DMOS transistor 100 further includes a gate oxide layer 130 that touches p− body region 112 over channel region 126, and a gate 132 that touches gate oxide layer 130 over channel region 126. Gate 132 can be implemented with metal or doped polysilicon.
In operation, a first positive voltage is placed on n+ drain region 120 and a second positive voltage is placed on gate 132, while ground is placed on n+ source region 122 and p+ contact region 124. In response to these bias conditions, the channel region 126 of p− body region 112 inverts, and electrons flow from n+ source region 122 to n+ drain region 120.
One important characteristic of a DMOS transistor is the breakdown voltage BVdss of the transistor, which is the maximum off-state voltage which can be placed on n+ drain region 120 before the drift region 114-to-body region 112 junction breaks down, or insulator layer 106 breaks down, whichever is lower. Since DMOS transistors are power transistors, there is a need to handle larger voltages and, thereby, a need to increase the breakdown voltage BVdss of the transistor.
U.S. Pat. No. 6,703,684 to Udrea et al teaches that the breakdown voltage BVdss of a lateral DMOS transistor can be increased by removing the portion of bulk region 104 that lies below the DMOS transistor. FIG. 2 shows a cross-sectional diagram that illustrates an example of a conventional Udrea DMOS transistor 200.
Udrea DMOS transistor 200 is similar to DMOS transistor 100 and, as a result, utilizes the same reference numerals to designate the structures that are common to both DMOS transistors. As shown in FIG. 2, Udrea DMOS transistor 200 differs from DMOS transistor 100 in that Udrea DMOS transistor 200 has a backside opening 210 that extends through bulk region 104 to expose the portion of insulator layer 106 that lies below DMOS transistor 200.
However, although Udrea transistor 200 increases the breakdown voltage BVdss of the transistor, backside trench etching significantly complicates the process flow, requires thick SOI wafers for the etch to stop on, and may require large capital outlays to purchase the equipment required for the process flow.